[VerilogA] Inverter with amplitude noise and can read power voltage in transient analysis

////////   Running 2019/01/20   //////////

`include "constants.vams"

`include "disciplines.vams"

// inverter

module inv_va_p_n(out, in, dd);

output out; voltage out;

input in; voltage in;

input dd; voltage dd;

parameter real td = 0 from [0:inf);     // delay to start of output transition

parameter real tt = 0 from [0:inf);     // transition time of output signals

parameter real vn=100u   ;// Noise RMS value

integer lout,seed;

real dv ;

analog begin

@ (initial_step) 

        begin

dv = vn*$rdist_normal(seed,0,1);

                        seed=555;

       end

    // make sure simulator sees the threshold crossing

    @(cross(V(in) - (V(dd)/2+dv)));

      begin

        // compute the logical value of the output

        if (V(in) > (V(dd)+dv)/2)

           lout = 0;

        else

           lout = 1;

       // update noise value

        dv = vn*$rdist_normal(seed,0,1);

     end

// create an analog version of logical output

    V(out) <+ V(dd)*transition(lout, td, tt);

end

endmodule